1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to a gate driving circuit of an active-matrix LCD.
2. Discussion of the Related Art
With reference to the attached drawings, a conventional gate driving circuit of LCD will now be described. As illustrated in FIG. 1, a conventional active-matrix panel includes a pixel array 1, a data driver 2, and a gate driver 3. Two clock signals .phi.1' and .phi.2', a horizontal start signal HST are input to the data driver 2 to produce data driving signals. Red (R), green (G) and blue(B) data signals are input to the pixel array 1 through passgate transistors by the data driving signals. Two clock signals .phi.1 and .phi.2 and a vertical start signal VST are input to the gate driver 3 to produce gate driving signals.
As illustrated in FIG. 2A, which is a conventional gate driving circuit, two clock inverters, a NAND gate, and four inverters are used for every stage.
As shown in the driving waveform of FIG. 2B, Q1 and Q2 overlap as illustrated because voltage Vdd is applied to the NAND gate of the first stage. Q2, Q3 and Q4 do not overlap each other because the signal from the previous terminal is applied to the corresponding NAND gates. That is, when signal VST is applied and signal .phi.2 is at a HIGH level, Q1 is at a HIGH level so that Q1 maintains the high level until .phi.2 becomes HIGH in the next time period. When .phi.1 becomes HIGH, Q2 is at a HIGH level. Here, Q2 maintains the high state until .phi.2 attains a high level. This is a typical characteristic of the NAND gate. That is, because the other input of the NAND gate is in a LOW state when .phi.2 is in a HIGH state, the output of the NAND gate is in a HIGH state, and as a result, the Q2 is changed to a LOW state when .phi.2 becomes HIGH. Q3 and Q4 are in their HIGH states without being overlapped with Q2.
As illustrated in FIG. 3A, the data driving circuit operates in the same manner as the gate driving circuit of FIG. 2A. That is, the output of the shift register serving as the data driver of each terminal is applied to the passgate transistor, thereby reading the R, G, B data in order to apply the R, G, B data to the data line.
Referring to FIG. 3B, the data driving waveform shows that the waveforms of Q1', Q2', Q3' and Q4' overlap one another. This prolongs the time to read the R, G, B data so as to be unaffected by TFT performance. Accordingly, even when the carrier mobility in the TFT is low, the shift register 2 serving as the data driver has sufficient time to read the data.
However, the conventional LCD gate driving circuit, as discussed above, has many defects due to a large number of TFTs forming the gate driver. The size of the panel is also increased by the large number of TFTs. The additional clock signals .phi.1 and .phi.2 required to operate the gate driver increase the cost. Furthermore, a .DELTA.Vp may exist for each pixel.
The .DELTA.Vp will be explained referring to FIGS. 4A and 4B. FIG. 4A is a diagram showing a conventional pixel array, and FIG.4B is a diagram showing a relationship between a gate voltage Vg and pixel charge voltages Vd and Vd'. In FIG.4A, Vcom is a voltage applied to the upper plate of a liquid crystal display, Ct is a pixel capacitance, and Cgs is a parasitic capacitance between the gate and the source of a TFT. The pixel capacitance Ct includes a liquid crystal capacitance Clc and a storage capacitance Cst. The .DELTA.Vp appears for a data value Vd charged in the pixel capacitance Ct, when the voltage Vg being applied to the gate changes to an OFF state from an ON state, where the pixel capacitance Ct is too small at the falling edge of the gate voltage Vg. The .DELTA.Vp can be expressed according to equation (1) below. EQU .DELTA.Vp=Cgs Vg/(Ct+Cgs) . . . (1)
As shown in FIG.4B, the data value Vd charged in the pixel capacitance decreases by .DELTA.Vp. Therefore, the data value Vd becomes Vd'. In general, it is possible to reduce .DELTA.Vp by increasing the pixel capacitance Ct. However, the amount of Ct that can be increased is limited and increasing Ct much greater than Cgs is difficult. The resultant value Vd' is different from the desired Vd by .DELTA.Vp, thereby affecting the picture quality of the liquid crystal display.